1. Field of the Invention
The present invention relates to initialising asynchronous latch chains as they occur for example with a DDR-(double data rate), a DDR2-RAM or another asynchronous RAM.
2. Description of Prior Art
Since the beginning of digital circuit technology the synchronous circuit design has gained priority over the asynchronous circuit design, for which especially the rapid development in microprocessor technology is responsible, which is based on synchronous circuit technology. Synchronous circuits work like a clocked finite states machine, wherein the states of the logical gates change synchronously and/or always at the same time. Synchronous circuitries are consequently known for a simple circuit design and a test of the design is reduced to a test of the delays of the combinatorial logical functions between the respective registers of the synchronous circuit.
In recent times it has been found, however, that the synchronous circuit design reaches fundamental boundaries, which cannot be solved using synchronous clocking. A first problem is that a circuit can only work synchronously if all its members maintain the clock at least up to a certain degree at the same time. The clock signals are however electrical signals and subject to the same delays as other signals when they spread over wires. If the delay amounts to a significant part of a clock cycle period for a certain part of the circuit, this part of the circuit cannot be regarded as working synchronously with the other parts of the circuit any more.
This problem is especially underlined by the fact that the complexity of circuitries of today's integrated circuits continuously increases, whereby the length of the electric signal paths between different circuit parts is increased.
A further problem of synchronous circuit design lies in the development of heat. With the CMOS-technology the gates for example merely consume energy during switching. As, however, the whole circuit is clocked by a single clock there are many gates, merely switching as they are connected to the clock but not because they process data. Consequently also currently inactive circuit portions consume energy with the synchronous circuits design, which is a disadvantage especially with multi-functional circuits.
The problem of a global clock is solved by an asynchronous circuit design wherein data are not processed by a global clock. Among the different approaches for realising an asynchronous clocking there exists for example one wherein data are transferred via so-called micro-pipelines and thereby captured by latch controllers at different points within the chip and stored temporarily to be released only if the next latch controller stage for receiving data is ready. This way asynchronous latch chains are formed with data being passed on using an acknowledge protocol.
At the beginning of an asynchronous latch chain an internal clock must be produced for taking over data from an external clock for data to be accepted. This clock generation, taking place during initialising the asynchronous latch chain, for example occurs during the circuit switch-on process and is critical for a safe later operation of the asynchronous latch chain.